1. Field of the Invention
This invention relates to unity gain buffer amplifiers, and more particularly to increasing the permissible input slew rate of such amplifiers by charging parasitic capacitances associated with the amplifier circuitry.
2. Description of the Related Art
Unity gain buffer amplifiers have been in use for applications such as the input stage for current feedback operational amplifiers, and stand-alone buffers. A simplified schematic diagram of such a circuit, used in the OP260 dual high-speed current-feedback operational amplifier by the PMI division of Analog Devices, Inc., the assignee of the present invention, is shown in FIG. 1. It includes an input branch with input bipolar transistors Q1 and Q2, which are respectively npn and pnp devices. An input terminal T1 is connected to the bases of each of the input transistors. The collector of Q1 is connected to a positive voltage bus V+, with a current source I1 drawing current from the emitter of Q1 to a negative voltage bus V-; the collector of Q2 is connected to V-, with another current source I2 supplying the Q2 emitter with current from V+. The current sources are typically transistors biased to supply about 0.5 mA, while the absolute voltage levels of the voltage buses can range from about 5 to about 15 volts.
An output branch consisting of series-connected npn and pnp transistors Q3 and Q4 is connected between V+ and V-, with an output terminal T2 taken from the common connection of the Q3, Q4 emitters. The base of Q3 is supplied with current from I2, while current is drawn from the base of Q4 by I1. The emitters of Q1 and Q2 are connected respectively to the bases of Q4 and Q3 by connector lines 2 and 4. The amplifier's unity gain between T1 and T2 results from the rough balancing of the base-emitter voltage drops across Q1 and Q4, and across Q2 and Q3.
The slew rate (the rate at which the circuit responds to a change in the input voltage) of the amplifier as described thus far is limited due to the presence of parasitic capacitances in the circuit, illustrated as capacitances C.sub.p1 and C.sub.p2 at the bases of Q3 and Q4, respectively. These parasitic capacitances result mainly from the collector-base capacitances of Q3 and Q4, the collector-base and collector-substrate capacitances of I1 and I2 (which are typically implemented by current source transistors), and metallization capacitances. The slew rate for a positive-going input signal at T1 is limited to I2/C.sub.p1, while the slew rate for a negative-going input signal is limited to I1/C.sub.p2. Simply making I1 and I2 larger would not be effective in speeding up the slew rate, since it would impose excessive currents upon Q1-Q4.
Instead of attempting to increase I1 and I2, current boosting npn and pnp bipolar transistors Q5 and Q6 are added in the OP260 device, each with its base connected to the input terminal T1. The base-emitter circuit of Q5 transmits current from V+ to the parasitic capacitance C.sub.p1, while the collector-emitter circuit of Q6 conducts current away from C.sub.p2 to V-. Q5 is gated into conduction when the input voltage at T1 is greater than about 2 base-emitter voltage drops (about 1.2 volts) greater than the output voltage at T2, while Q6 is gated into conduction when the input voltage drops more than about 2 base-emitter voltage drops below the output voltage. When gated, Q5 provides for a more rapid charging of C.sub.p1, while Q6 increases the negative charging (i.e., the discharge) rate for C.sub.p2.
While the addition of Q5 and Q6 provides a gross improvement in the input slew rate, it does not speed up the circuit operation for small signal levels. In fact, the circuit response for small signals is actually slower because of additional stray capacitances introduced by Q5 and Q6.